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authorStephen Warren <swarren@nvidia.com>2013-08-09 16:49:29 +0200
committerStephen Warren <swarren@nvidia.com>2013-08-12 22:20:36 +0200
commit44fefab459cfb78c446a8b7cc4bbf622d5b97396 (patch)
tree4cb4d0535b02887b879ab3996445b5279131e2bc /arch/arm/boot/dts
parentARM: tegra: Enable PCIe controller on Beaver (diff)
downloadlinux-44fefab459cfb78c446a8b7cc4bbf622d5b97396.tar.xz
linux-44fefab459cfb78c446a8b7cc4bbf622d5b97396.zip
ARM: tegra: Fix Beaver's PCIe lane configuration
Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used, and the only way those align is with a x2 x2 x2 configuration. Also, disable root port 1; there's nothing connected to it. Root port 0 is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 21660da2ec59..51a0ee7b0c85 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -18,16 +18,16 @@
pci@1,0 {
status = "okay";
- nvidia,num-lanes = <4>;
+ nvidia,num-lanes = <2>;
};
pci@2,0 {
- status = "okay";
- nvidia,num-lanes = <1>;
+ nvidia,num-lanes = <2>;
};
pci@3,0 {
- nvidia,num-lanes = <1>;
+ status = "okay";
+ nvidia,num-lanes = <2>;
};
};