diff options
| author | Poddar, Sourav <sourav.poddar@ti.com> | 2014-04-29 10:34:20 +0200 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2014-05-23 10:50:36 +0200 |
| commit | 9e100ebafb913c7bedfbfc0e0e1f97b3e43d8a4c (patch) | |
| tree | 54f91555276af48c15f1f1f7f748a1d1f1ec2cd9 /arch/arm/boot | |
| parent | ARM: dts: set 'ti,set-rate-parent' for dpll4_m5 path (diff) | |
| download | linux-9e100ebafb913c7bedfbfc0e0e1f97b3e43d8a4c.tar.xz linux-9e100ebafb913c7bedfbfc0e0e1f97b3e43d8a4c.zip | |
ARM: dts: am33xx-clock: Fix ehrpwm tbclk data
tbclk does not need to be a composite clock, we can simply
use gate clock for this purpose.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/am33xx-clocks.dtsi | 30 |
1 files changed, 6 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 9ccfe508dea2..712edce7d6fb 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -96,47 +96,29 @@ clock-div = <1>; }; - ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "ti,gate-clock"; clocks = <&dpll_per_m2_ck>; ti,bit-shift = <0>; reg = <0x0664>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm0_gate_tbclk>; - }; - - ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "ti,gate-clock"; clocks = <&dpll_per_m2_ck>; ti,bit-shift = <1>; reg = <0x0664>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm1_gate_tbclk>; - }; - - ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "ti,gate-clock"; clocks = <&dpll_per_m2_ck>; ti,bit-shift = <2>; reg = <0x0664>; }; - - ehrpwm2_tbclk: ehrpwm2_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm2_gate_tbclk>; - }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck { |