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| author | Thomas Gleixner <[tglx@linutronix.de]> | 2010-07-31 17:36:06 +0200 |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2010-10-26 08:09:56 +0200 |
| commit | ae360a78f41164e7f9c4cf846696b5b6d8dae5c8 (patch) | |
| tree | cb96d4ecbb0c04e7c25a0b08b2dc7f979391a1dc /arch/arm/kernel/machine_kexec.c | |
| parent | ARM: Improve the L2 cache performance when PL310 is used (diff) | |
| download | linux-ae360a78f41164e7f9c4cf846696b5b6d8dae5c8.tar.xz linux-ae360a78f41164e7f9c4cf846696b5b6d8dae5c8.zip | |
arm: Disable outer (L2) cache in kexec
kexec does not disable the outer cache before disabling the inner
caches in cpu_proc_fin(). So L2 is enabled across the kexec jump. When
the new kernel enables chaches again, it randomly crashes.
Disabling L2 before calling cpu_proc_fin() cures the problem.
Disabling L2 requires the following new functions: flush_all(),
inv_all() and disable(). Add them to outer_cache_fns and call them
from the kexec code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Diffstat (limited to 'arch/arm/kernel/machine_kexec.c')
| -rw-r--r-- | arch/arm/kernel/machine_kexec.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index 1fc74cbd1a19..3a8fd5140d7a 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -78,7 +78,10 @@ void machine_kexec(struct kimage *image) local_fiq_disable(); setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ flush_cache_all(); + outer_flush_all(); + outer_disable(); cpu_proc_fin(); + outer_inv_all(); flush_cache_all(); cpu_reset(reboot_code_buffer_phys); } |