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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2015-03-12 09:06:30 +0100
committerSekhar Nori <nsekhar@ti.com>2015-03-18 12:47:36 +0100
commitb38434145b341c148b8d98cfbfc1e87bb4d9e2d9 (patch)
treee67a0ef7589fb46e0a9f7d8ab915144dd6102eb0 /arch/arm/mach-davinci/include
parentARM: davinci: dm646x: Clean up the McASP DMA resources (diff)
downloadlinux-b38434145b341c148b8d98cfbfc1e87bb4d9e2d9.tar.xz
linux-b38434145b341c148b8d98cfbfc1e87bb4d9e2d9.zip
ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
McASP1 TX interrupt is 30, not 32 on DM646x DMSoC. While at it remove the bogus AEMIF interrupt entry from dm646x_default_priorities[]. AEMIF interrupt on DM6467 is 60 not 30 and the entry for the correct interrupt number is already present in the same table. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> [nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/mach-davinci/include')
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71798dc..edb2ca62321a 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -129,8 +129,8 @@
#define IRQ_DM646X_EMACMISCINT 27
#define IRQ_DM646X_MCASP0TXINT 28
#define IRQ_DM646X_MCASP0RXINT 29
+#define IRQ_DM646X_MCASP1TXINT 30
#define IRQ_DM646X_RESERVED_3 31
-#define IRQ_DM646X_MCASP1TXINT 32
#define IRQ_DM646X_VLQINT 38
#define IRQ_DM646X_UARTINT2 42
#define IRQ_DM646X_SPINT0 43