diff options
author | Arnd Bergmann <arnd@arndb.de> | 2015-01-30 10:45:33 +0100 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2015-12-01 21:52:50 +0100 |
commit | d8b2823e950cd9634eb4a01f563ee55afb39d549 (patch) | |
tree | f9999497cd91d54b312911939828e98c2f90ebe2 /arch/arm/mach-ks8695/include | |
parent | ARM: omap1: make headers more local (diff) | |
download | linux-d8b2823e950cd9634eb4a01f563ee55afb39d549.tar.xz linux-d8b2823e950cd9634eb4a01f563ee55afb39d549.zip |
ARM: ks8695: make headers more local
Some header files are never included outside of a mach-ks8695
directory and do not need to be made visible in include/mach,
so let's just move them all down one level.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/arm/mach-ks8695/include')
-rw-r--r-- | arch/arm/mach-ks8695/include/mach/devices.h | 32 | ||||
-rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-hpna.h | 25 | ||||
-rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-lan.h | 65 | ||||
-rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-mem.h | 89 | ||||
-rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-pci.h | 53 | ||||
-rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-sys.h | 34 | ||||
-rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-wan.h | 65 |
7 files changed, 0 insertions, 363 deletions
diff --git a/arch/arm/mach-ks8695/include/mach/devices.h b/arch/arm/mach-ks8695/include/mach/devices.h deleted file mode 100644 index 1e6594a0f297..000000000000 --- a/arch/arm/mach-ks8695/include/mach/devices.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/devices.h - * - * Copyright (C) 2006 Andrew Victor - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_DEVICES_H -#define __ASM_ARCH_DEVICES_H - -#include <linux/pci.h> - - /* Ethernet */ -extern void __init ks8695_add_device_wan(void); -extern void __init ks8695_add_device_lan(void); -extern void __init ks8695_add_device_hpna(void); - - /* PCI */ -#define KS8695_MODE_PCI 0 -#define KS8695_MODE_MINIPCI 1 -#define KS8695_MODE_CARDBUS 2 - -struct ks8695_pci_cfg { - short mode; - int (*map_irq)(const struct pci_dev *, u8, u8); -}; -extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-hpna.h b/arch/arm/mach-ks8695/include/mach/regs-hpna.h deleted file mode 100644 index 815ce5c2e3b9..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-hpna.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-wan.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - HPNA Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_HPNA_H -#define KS8695_HPNA_H - -#define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) -#define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) -#define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) - - -/* - * HPNA registers - */ - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-lan.h b/arch/arm/mach-ks8695/include/mach/regs-lan.h deleted file mode 100644 index 82c5f3791afb..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-lan.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-lan.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - LAN Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_LAN_H -#define KS8695_LAN_H - -#define KS8695_LAN_OFFSET (0xF0000 + 0x8000) -#define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) -#define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) - - -/* - * LAN registers - */ -#define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ -#define KS8695_LMDRXC (0x04) /* DMA Receive Control */ -#define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ -#define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ -#define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ -#define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ -#define KS8695_LMAL (0x18) /* MAC Station Address Low */ -#define KS8695_LMAH (0x1c) /* MAC Station Address High */ -#define KS8695_LMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ -#define KS8695_LMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ - - -/* DMA Transmit Control Register */ -#define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ -#define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ -#define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ -#define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ -#define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ -#define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ -#define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ -#define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ -#define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ -#define LMDTXC_LMTE (1 << 0) /* TX Enable */ - -/* DMA Receive Control Register */ -#define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ -#define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ -#define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ -#define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ -#define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ -#define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ -#define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ -#define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ -#define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ -#define LMDRXC_LMRA (1 << 2) /* Receive All */ -#define LMDRXC_LMRE (1 << 1) /* RX Enable */ - -/* Additional Station Address High */ -#define LMAAH_E (1 << 31) /* Address Enabled */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-mem.h b/arch/arm/mach-ks8695/include/mach/regs-mem.h deleted file mode 100644 index 55806bc68ce3..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-mem.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-mem.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - Memory Controller registers and bit definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_MEM_H -#define KS8695_MEM_H - -#define KS8695_MEM_OFFSET (0xF0000 + 0x4000) -#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) -#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) - - -/* - * Memory Controller Registers - */ -#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ -#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ -#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ -#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ -#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ -#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ -#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ -#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ -#define KS8695_SDGCON (0x38) /* SDRAM General Control */ -#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ -#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ - - -/* External I/O Access Control Registers */ -#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ -#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ -#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ -#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ -#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ -#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ - -/* ROM/SRAM/Flash Control Register */ -#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ -#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ -#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ -#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ -#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ -#define PMC_NORMAL (0 << 0) -#define PMC_4WORD (1 << 0) -#define PMC_8WORD (2 << 0) -#define PMC_16WORD (3 << 0) - -/* External I/O and ROM/SRAM/Flash General Register */ -#define ERGCON_TMULT (3 << 28) /* Time Multiplier */ -#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ -#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ -#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ -#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ -#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ - -/* SDRAM Control Register */ -#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ -#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ -#define SDCON_DBCAB (3 << 8) /* Column Address Bits */ -#define SDCON_DBBNUM (1 << 3) /* Number of Banks */ -#define SDCON_DBDBW (3 << 1) /* Data Bus Width */ - -/* SDRAM General Control Register */ -#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ -#define SDGCON_SDCAS (3 << 0) /* CAS latency */ - -/* SDRAM Buffer Control Register */ -#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ -#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ -#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ -#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ -#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ -#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ -#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ -#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ - -/* SDRAM Refresh Timer Register */ -#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-pci.h b/arch/arm/mach-ks8695/include/mach/regs-pci.h deleted file mode 100644 index 75a9db6edbd9..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-pci.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-pci.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - PCI bridge registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define KS8695_PCI_OFFSET (0xF0000 + 0x2000) -#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) -#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) - - -#define KS8695_CRCFID (0x000) /* Configuration: Identification */ -#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ -#define KS8695_CRCFRV (0x008) /* Configuration: Revision */ -#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ -#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ -#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ -#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ -#define KS8695_PBCA (0x100) /* Bridge Configuration Address */ -#define KS8695_PBCD (0x104) /* Bridge Configuration Data */ -#define KS8695_PBM (0x200) /* Bridge Mode */ -#define KS8695_PBCS (0x204) /* Bridge Control and Status */ -#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ -#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ -#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ -#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ -#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ -#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ -#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ -#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ - - -/* Configuration: Identification */ - -/* Configuration: Command and Status */ - -/* Configuration: Revision */ - - - -#define CFRV_GUEST (1 << 23) - -#define PBCA_TYPE1 (1) -#define PBCA_ENABLE (1 << 31) - - diff --git a/arch/arm/mach-ks8695/include/mach/regs-sys.h b/arch/arm/mach-ks8695/include/mach/regs-sys.h deleted file mode 100644 index 57c20be0c129..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-sys.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-sys.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - System control registers and bit definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_SYS_H -#define KS8695_SYS_H - -#define KS8695_SYS_OFFSET (0xF0000 + 0x0000) -#define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) -#define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) - - -#define KS8695_SYSCFG (0x00) /* System Configuration Register */ -#define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ - - -/* System Configuration Register */ -#define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ - -/* System Clock and Bus Control Register */ -#define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ -#define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-wan.h b/arch/arm/mach-ks8695/include/mach/regs-wan.h deleted file mode 100644 index c475bed22b8e..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-wan.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-wan.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - WAN Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_WAN_H -#define KS8695_WAN_H - -#define KS8695_WAN_OFFSET (0xF0000 + 0x6000) -#define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) -#define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) - - -/* - * WAN registers - */ -#define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ -#define KS8695_WMDRXC (0x04) /* DMA Receive Control */ -#define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ -#define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ -#define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ -#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ -#define KS8695_WMAL (0x18) /* MAC Station Address Low */ -#define KS8695_WMAH (0x1c) /* MAC Station Address High */ -#define KS8695_WMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ -#define KS8695_WMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ - - -/* DMA Transmit Control Register */ -#define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ -#define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ -#define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ -#define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ -#define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ -#define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ -#define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ -#define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ -#define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ -#define WMDTXC_WMTE (1 << 0) /* TX Enable */ - -/* DMA Receive Control Register */ -#define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ -#define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ -#define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ -#define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ -#define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ -#define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ -#define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ -#define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ -#define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ -#define WMDRXC_WMRA (1 << 2) /* Receive All */ -#define WMDRXC_WMRE (1 << 0) /* RX Enable */ - -/* Additional Station Address High */ -#define WMAAH_E (1 << 31) /* Address Enabled */ - - -#endif |