diff options
| author | Al Viro <viro@zeniv.linux.org.uk> | 2014-06-12 06:27:11 +0200 |
|---|---|---|
| committer | Al Viro <viro@zeniv.linux.org.uk> | 2014-06-12 06:28:09 +0200 |
| commit | 9c1d5284c79fea050f115eadeec1dd1758e5c630 (patch) | |
| tree | 4d16fd5aad7ff4931e985c0128c5747f23561f8a /arch/arm/mach-omap2/omap-headsmp.S | |
| parent | kill generic_file_splice_write() (diff) | |
| parent | dcache: add missing lockdep annotation (diff) | |
| download | linux-9c1d5284c79fea050f115eadeec1dd1758e5c630.tar.xz linux-9c1d5284c79fea050f115eadeec1dd1758e5c630.zip | |
Merge commit '9f12600fe425bc28f0ccba034a77783c09c15af4' into for-linus
Backmerge of dcache.c changes from mainline. It's that, or complete
rebase...
Conflicts:
fs/splice.c
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/omap-headsmp.S')
| -rw-r--r-- | arch/arm/mach-omap2/omap-headsmp.S | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 75e92952c18e..40c5d5f1451c 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -1,7 +1,7 @@ /* * Secondary CPU startup routine source file. * - * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009-2014 Texas Instruments, Inc. * * Author: * Santosh Shilimkar <santosh.shilimkar@ti.com> @@ -28,9 +28,13 @@ * code. This routine also provides a holding flag into which * secondary core is held until we're ready for it to initialise. * The primary core will update this flag using a hardware -+ * register AuxCoreBoot0. + * register AuxCoreBoot0. */ ENTRY(omap5_secondary_startup) +.arm +THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode. +THUMB( bx r9 ) @ If this is a Thumb-2 kernel, +THUMB( .thumb ) @ switch to Thumb now. wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] mov r0, r0, lsr #5 |