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authorEric Bénard <eric@eukrea.com>2010-07-21 14:46:11 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2010-07-26 15:05:21 +0200
commitaa8721431909c9afa611373c7edfb7f514a6ad83 (patch)
tree4202813835b9f9a151ffd961748cdff1db30752a /arch/arm/plat-mxc
parenteukrea_mbimx27-baseboard: fix compile when CONFIG_SPI_IMX is disabled (diff)
downloadlinux-aa8721431909c9afa611373c7edfb7f514a6ad83.tar.xz
linux-aa8721431909c9afa611373c7edfb7f514a6ad83.zip
i.MX51: handle IRQ for gpio 16..31
The i.MX51 generates 2 IRQ for each GPIO bank : one for gpio 0 to 15 and one for gpio 16 to 31. Actually only the lower IRQ is registered so register the second one. Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/gpio.c6
-rw-r--r--arch/arm/plat-mxc/include/mach/gpio.h1
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 71437c61cfd7..11dc06190b5d 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -292,6 +292,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
/* setup one handler for each entry */
set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
set_irq_data(port[i].irq, &port[i]);
+ if (port[i].irq_high) {
+ /* setup handler for GPIO 16 to 31 */
+ set_irq_chained_handler(port[i].irq_high,
+ mx3_gpio_irq_handler);
+ set_irq_data(port[i].irq_high, &port[i]);
+ }
}
}
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 894d2f87c856..9541ecbfd22c 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -33,6 +33,7 @@
struct mxc_gpio_port {
void __iomem *base;
int irq;
+ int irq_high;
int virtual_irq_start;
struct gpio_chip chip;
u32 both_edges;