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| author | Xingyu Chen <xingyu.chen@amlogic.com> | 2017-11-16 10:01:14 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-12-06 21:00:05 +0100 |
| commit | e102da498ec3001009433d8d2d160eebbe6d1d69 (patch) | |
| tree | 109a24c29453488b7619c4c0f9ed6903a79b64f4 /arch/arm64/boot/dts/amlogic | |
| parent | ARM64: dts: odroid-c2: Add HDMI and CEC Nodes (diff) | |
| download | linux-e102da498ec3001009433d8d2d160eebbe6d1d69.tar.xz linux-e102da498ec3001009433d8d2d160eebbe6d1d69.zip | |
ARM64: dts: meson: drop "sana" clock from SAR ADC
The SAR ADC modules doesn't require The "sana" clock.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Singed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 6904872f08af..eeaf10c7ba74 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -740,10 +740,9 @@ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, <&clkc CLKID_SAR_ADC_CLK>, <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; }; &sd_emmc_a { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 49b8ec159603..4a316a11a00e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -690,10 +690,9 @@ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, <&clkc CLKID_SAR_ADC_CLK>, <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; }; &sd_emmc_a { |