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authorAkhil R <akhilrajeev@nvidia.com>2022-11-10 18:17:47 +0100
committerThierry Reding <treding@nvidia.com>2022-11-21 13:30:13 +0100
commitdd0be8278ab9675d168390c990110f8d2f62ca38 (patch)
tree4f7ad1afc1943ceaae616a7d14967ad00814e31b /arch/arm64/boot/dts/nvidia/tegra194.dtsi
parentarm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller (diff)
downloadlinux-dd0be8278ab9675d168390c990110f8d2f62ca38.tar.xz
linux-dd0be8278ab9675d168390c990110f8d2f62ca38.zip
arm64: tegra: Add dma-channel-mask in GPCDMA node
Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra194.dtsi')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c6c10580e664..a6721bb82bbd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -143,7 +143,8 @@
reg = <0x2600000 0x210000>;
resets = <&bpmp TEGRA194_RESET_GPCDMA>;
reset-names = "gpcdma";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -177,6 +178,7 @@
#dma-cells = <1>;
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
+ dma-channel-mask = <0xfffffffe>;
status = "okay";
};