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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-11-24 19:43:21 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2022-12-27 19:07:01 +0100 |
| commit | 47603d621e68011c70e5d3e5dbbe196c82d104d4 (patch) | |
| tree | 707bf6a34d0f15a1010e4bdbe2faeea1fc6e60c2 /arch/arm64/boot/dts/qcom/sc7180-idp.dts | |
| parent | arm64: dts: qcom: qcs404: align CDSP PAS node with bindings (diff) | |
| download | linux-47603d621e68011c70e5d3e5dbbe196c82d104d4.tar.xz linux-47603d621e68011c70e5d3e5dbbe196c82d104d4.zip | |
arm64: dts: qcom: sc7180: align MPSS PAS node with bindings
The SC7180 MPSS/MSS remote processor can be brought to life using two
different bindings:
1. qcom,sc7180-mpss-pas - currently used in DTSI
2. qcom,sc7180-mss-pil
Move the properties related to qcom,sc7180-mss-pil (qcom,halt-regs,
qcom,spare-regs, resets, additional clocks and regs) to specific boards
using the PIL, to silence DT schema warnings.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221124184333.133911-4-krzysztof.kozlowski@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7180-idp.dts')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180-idp.dts | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 70fd9ff8dfa2..b27b5f0e2b6b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -370,8 +370,26 @@ &remoteproc_mpss { status = "okay"; compatible = "qcom,sc7180-mss-pil"; + reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo"; + iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; memory-region = <&mba_mem &mpss_mem>; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; }; &sdhc_1 { |