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authorMark Hasemeyer <markhas@chromium.org>2024-01-02 22:07:39 +0100
committerBjorn Andersson <andersson@kernel.org>2024-02-14 06:37:17 +0100
commita4b28b9ecc99673da875e214b1a06f1e0f0a24fa (patch)
treeca3ca9b2b2bd232c8b0959d81973de0733ec4e27 /arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
parentarm64: dts: qcom: sc7180: Enable cros-ec-spi as wake source (diff)
downloadlinux-a4b28b9ecc99673da875e214b1a06f1e0f0a24fa.tar.xz
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arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Mark Hasemeyer <markhas@chromium.org> Link: https://lore.kernel.org/r/20240102140734.v4.15.I7ea3f53272c9b7cd77633adfd18058ba443eed96@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index 9ea6636125ad..2ba4ea60cb14 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -548,6 +548,7 @@ ap_ec_spi: &spi10 {
pinctrl-names = "default";
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
+ wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";