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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-04-12 13:27:32 +0200 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2023-04-12 14:43:04 +0200 |
| commit | 0dd58c077325b4260aa87e9db256d41806c2c9c5 (patch) | |
| tree | c3fd4761293a2790af0dc646c1d5b4cd68e73a9a /arch/arm64/boot | |
| parent | arm64: dts: mediatek: mt8173: correct GPIO keys wakeup (diff) | |
| download | linux-0dd58c077325b4260aa87e9db256d41806c2c9c5.tar.xz linux-0dd58c077325b4260aa87e9db256d41806c2c9c5.zip | |
arm64: dts: mediatek: mt6795: Add tertiary PWM node
The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is
not display specific and can be used as a generic PWM controller.
This node is left disabled as usage is board-specific.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230412112739.160376-21-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt6795.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 090400d7fd61..17019fbea0af 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -524,6 +524,25 @@ status = "disabled"; }; + pwm2: pwm@11006000 { + compatible = "mediatek,mt6795-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>, + <&pericfg CLK_PERI_PWM6>, + <&pericfg CLK_PERI_PWM7>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5", "pwm6", "pwm7"; + status = "disabled"; + }; + i2c0: i2c@11007000 { compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; |