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| author | Nícolas F. R. A. Prado <nfraprado@collabora.com> | 2024-06-06 23:12:04 +0200 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-07-30 16:36:56 +0200 |
| commit | 587c945c933364f24d132918d7703997fd1e2cd6 (patch) | |
| tree | 849db3ec839e2c57b559b77a0b652924020f7e29 /arch/arm64/boot | |
| parent | arm64: dts: mediatek: mt8183-kukui-jacuzzi: Simplify DSI endpoint replacement (diff) | |
| download | linux-587c945c933364f24d132918d7703997fd1e2cd6.tar.xz linux-587c945c933364f24d132918d7703997fd1e2cd6.zip | |
arm64: dts: mediatek: mt8195: Add SCP phandle to MDP3 DMA controller
While the MDP3 DMA controller can look for the SCP node based on
compatible, it's best practice to supply the MDP3 node with a phandle to
the SCP since that allows supporting dual core SCP as well. Besides,
relying on the compatible search causes an error to be printed, since
the phandle is tried first:
mtk-mdp3 14001000.dma-controller: can't get SCP node
Add the missing phandle to follow the best practice and get rid of the
error.
Fixes: 5710462a116c ("arm64: dts: mediatek: mt8195: add MDP3 nodes")
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20240606-mt8195-dma-scp-node-err-v2-1-e14702e9d3f2@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 2ee45752583c..a46062258603 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2037,6 +2037,7 @@ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; + mediatek,scp = <&scp>; power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; |