diff options
| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2023-10-19 07:40:18 +0200 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2023-10-19 12:16:32 +0200 |
| commit | 7287d423f1388ddfdc5bd1dd6b9f6aa659ef3bbd (patch) | |
| tree | e84ae3a5235b316373cb48338270980d5da297b3 /arch/arm64/boot | |
| parent | arm64: dts: ti: k3-j712s2-mcu: Add the mcu domain watchdog instances (diff) | |
| download | linux-7287d423f1388ddfdc5bd1dd6b9f6aa659ef3bbd.tar.xz linux-7287d423f1388ddfdc5bd1dd6b9f6aa659ef3bbd.zip | |
arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: Fix serdes_ln_ctrl node]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20231019054022.175163-2-j-choudhary@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 6ca80d16ee78..d65788d16e22 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,10 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/mux/mux.h> + +#include "k3-serdes.h" + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +30,42 @@ }; }; + scm_conf: bus@100000 { + compatible = "simple-bus"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x00004080 0x30>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, + <J784S4_SERDES0_LANE1_PCIE1_LANE1>, + <J784S4_SERDES0_LANE2_IP3_UNUSED>, + <J784S4_SERDES0_LANE3_USB>, + <J784S4_SERDES1_LANE0_PCIE0_LANE0>, + <J784S4_SERDES1_LANE1_PCIE0_LANE1>, + <J784S4_SERDES1_LANE2_PCIE0_LANE2>, + <J784S4_SERDES1_LANE3_PCIE0_LANE3>, + <J784S4_SERDES2_LANE0_IP2_UNUSED>, + <J784S4_SERDES2_LANE1_IP2_UNUSED>, + <J784S4_SERDES2_LANE2_QSGMII_LANE1>, + <J784S4_SERDES2_LANE3_QSGMII_LANE2>, + <J784S4_SERDES4_LANE0_EDP_LANE0>, + <J784S4_SERDES4_LANE1_EDP_LANE1>, + <J784S4_SERDES4_LANE2_EDP_LANE2>, + <J784S4_SERDES4_LANE3_EDP_LANE3>; + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; |