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authorCatalin Marinas <catalin.marinas@arm.com>2016-11-29 16:38:57 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2016-11-29 16:38:57 +0100
commit00cc2e07453796dc99a32c390ded964f33ac7e89 (patch)
tree3021c842270e2873e7ae4b183000dc8c0c7012b7 /arch/arm64/include
parentarm64: head.S: Fix CNTHCTL_EL2 access on VHE system (diff)
parentselftests: arm64: add test for unaligned/inexact watchpoint handling (diff)
downloadlinux-00cc2e07453796dc99a32c390ded964f33ac7e89.tar.xz
linux-00cc2e07453796dc99a32c390ded964f33ac7e89.zip
Merge Will Deacon's for-next/perf branch into for-next/core
* will/for-next/perf: selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses arm64: Allow hw watchpoint at varied offset from base address hw_breakpoint: Allow watchpoint of length 3,5,6 and 7
Diffstat (limited to 'arch/arm64/include')
-rw-r--r--arch/arm64/include/asm/hw_breakpoint.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index 9510ace570e2..b6b167ac082b 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -77,7 +77,11 @@ static inline void decode_ctrl_reg(u32 reg,
/* Lengths */
#define ARM_BREAKPOINT_LEN_1 0x1
#define ARM_BREAKPOINT_LEN_2 0x3
+#define ARM_BREAKPOINT_LEN_3 0x7
#define ARM_BREAKPOINT_LEN_4 0xf
+#define ARM_BREAKPOINT_LEN_5 0x1f
+#define ARM_BREAKPOINT_LEN_6 0x3f
+#define ARM_BREAKPOINT_LEN_7 0x7f
#define ARM_BREAKPOINT_LEN_8 0xff
/* Kernel stepping */
@@ -119,7 +123,7 @@ struct perf_event;
struct pmu;
extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
- int *gen_len, int *gen_type);
+ int *gen_len, int *gen_type, int *offset);
extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,