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| author | James Morse <james.morse@arm.com> | 2019-10-17 19:42:59 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2019-10-25 18:48:44 +0200 |
| commit | ee9d90be9ddace01b7fb126567e4b539fbe1f82f (patch) | |
| tree | e0776d49cff3e0ff4259ee3c853c64d6bce31c3d /arch/arm64/kernel/traps.c | |
| parent | arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419 (diff) | |
| download | linux-ee9d90be9ddace01b7fb126567e4b539fbe1f82f.tar.xz linux-ee9d90be9ddace01b7fb126567e4b539fbe1f82f.zip | |
arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419
Systems affected by Neoverse-N1 #1542419 support DIC so do not need to
perform icache maintenance once new instructions are cleaned to the PoU.
For the errata workaround, the kernel hides DIC from user-space, so that
the unnecessary cache maintenance can be trapped by firmware.
To reduce the number of traps, produce a fake IminLine value based on
PAGE_SIZE.
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel/traps.c')
| -rw-r--r-- | arch/arm64/kernel/traps.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 465f0a0f8f0a..4e3e9d9c8151 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -470,9 +470,15 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) int rt = ESR_ELx_SYS64_ISS_RT(esr); unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); - if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) + if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { + /* Hide DIC so that we can trap the unnecessary maintenance...*/ val &= ~BIT(CTR_DIC_SHIFT); + /* ... and fake IminLine to reduce the number of traps. */ + val &= ~CTR_IMINLINE_MASK; + val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; + } + pt_regs_write_reg(regs, rt, val); arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |