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| author | Marc Zyngier <marc.zyngier@arm.com> | 2015-06-11 19:50:17 +0200 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2015-06-17 10:59:55 +0200 |
| commit | 4642019dc4457486223e1fb75a6a4cba6e0e903a (patch) | |
| tree | 5bf3859158f850815b990e6ab8c57376d4748250 /arch/arm64/kvm/vgic-v3-switch.S | |
| parent | KVM: arm: vgic: Drop useless Group0 warning (diff) | |
| download | linux-4642019dc4457486223e1fb75a6a4cba6e0e903a.tar.xz linux-4642019dc4457486223e1fb75a6a4cba6e0e903a.zip | |
arm/arm64: KVM: vgic: Do not save GICH_HCR / ICH_HCR_EL2
The GIC Hypervisor Configuration Register is used to enable
the delivery of virtual interupts to a guest, as well as to
define in which conditions maintenance interrupts are delivered
to the host.
This register doesn't contain any information that we need to
read back (the EOIcount is utterly useless for us).
So let's save ourselves some cycles, and not save it before
writing zero to it.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/kvm/vgic-v3-switch.S')
| -rw-r--r-- | arch/arm64/kvm/vgic-v3-switch.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm64/kvm/vgic-v3-switch.S b/arch/arm64/kvm/vgic-v3-switch.S index 617a012a0107..3c20730ddff5 100644 --- a/arch/arm64/kvm/vgic-v3-switch.S +++ b/arch/arm64/kvm/vgic-v3-switch.S @@ -48,13 +48,11 @@ dsb st // Save all interesting registers - mrs_s x4, ICH_HCR_EL2 mrs_s x5, ICH_VMCR_EL2 mrs_s x6, ICH_MISR_EL2 mrs_s x7, ICH_EISR_EL2 mrs_s x8, ICH_ELSR_EL2 - str w4, [x3, #VGIC_V3_CPU_HCR] str w5, [x3, #VGIC_V3_CPU_VMCR] str w6, [x3, #VGIC_V3_CPU_MISR] str w7, [x3, #VGIC_V3_CPU_EISR] |