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| author | Tiezhu Yang <yangtiezhu@loongson.cn> | 2023-12-09 08:49:16 +0100 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2023-12-09 08:49:16 +0100 |
| commit | 772cbe948fb07389639d4e698a2d3299f8e538b8 (patch) | |
| tree | c6382a817363ec69c522b955a705bdd546d86983 /arch/loongarch/net/bpf_jit.c | |
| parent | LoongArch: BPF: Don't sign extend function return value (diff) | |
| download | linux-772cbe948fb07389639d4e698a2d3299f8e538b8.tar.xz linux-772cbe948fb07389639d4e698a2d3299f8e538b8.zip | |
LoongArch: BPF: Fix sign-extension mov instructions
We can see that "Short form of movsx, dst_reg = (s8,s16,s32)src_reg" in
include/linux/filter.h, additionally, for BPF_ALU64 the value of the
destination register is unchanged whereas for BPF_ALU the upper 32 bits
of the destination register are zeroed, so it should clear the upper 32
bits for BPF_ALU.
[root@linux fedora]# echo 1 > /proc/sys/net/core/bpf_jit_enable
[root@linux fedora]# modprobe test_bpf
Before:
test_bpf: #81 ALU_MOVSX | BPF_B jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times)
test_bpf: #82 ALU_MOVSX | BPF_H jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times)
After:
test_bpf: #81 ALU_MOVSX | BPF_B jited:1 6 PASS
test_bpf: #82 ALU_MOVSX | BPF_H jited:1 6 PASS
By the way, the bpf selftest case "./test_progs -t verifier_movsx" can
also be fixed with this patch.
Fixes: f48012f16150 ("LoongArch: BPF: Support sign-extension mov instructions")
Acked-by: Hengqi Chen <hengqi.chen@gmail.com>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/net/bpf_jit.c')
| -rw-r--r-- | arch/loongarch/net/bpf_jit.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c index d76281efc5b8..cd002f183648 100644 --- a/arch/loongarch/net/bpf_jit.c +++ b/arch/loongarch/net/bpf_jit.c @@ -480,10 +480,12 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext case 8: move_reg(ctx, t1, src); emit_insn(ctx, extwb, dst, t1); + emit_zext_32(ctx, dst, is32); break; case 16: move_reg(ctx, t1, src); emit_insn(ctx, extwh, dst, t1); + emit_zext_32(ctx, dst, is32); break; case 32: emit_insn(ctx, addw, dst, src, LOONGARCH_GPR_ZERO); |