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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:44 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:23:38 +0200 |
| commit | 5e5b6527128cea50f12a7064bf61b130b3a2739a (patch) | |
| tree | 6dcaaf2a258785705bacc2447f4f639f575aa4c6 /arch/mips/include/asm/mach-cavium-octeon/war.h | |
| parent | MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option (diff) | |
| download | linux-5e5b6527128cea50f12a7064bf61b130b3a2739a.tar.xz linux-5e5b6527128cea50f12a7064bf61b130b3a2739a.zip | |
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon/war.h')
| -rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/war.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h index 1e01e2f20086..915ce0352c20 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/war.h +++ b/arch/mips/include/asm/mach-cavium-octeon/war.h @@ -9,7 +9,6 @@ #ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H -#define R4600_V1_HIT_CACHEOP_WAR 0 #define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 |