MIPS: Add generic CM probe & access code

The kernel currently only probes for a MIPS Coherence Manager in the
Malta interrupt code in order to detect & enable the GIC. However CM is
not Malta-specific, so this should really be more generic. This patch
introduces some non-Malta-specific code which probes for a CM and
performs some basic initialisation.

A new header, with temporarily duplicated register definitions, is
introduced in order to:

  1) Allow the new definitions to be correct with regards to the
     CM documentation, as many of those in gcmpregs.h aren't.

  2) Allow switching away from the REG() macro used via a few layers of
     nested macros in order to access registers in gcmpregs.h. This
     patch instead introduced accessor functions akin to the
     {read,write}_c0_* functions used for cop0 registers.

  3) Allow users of the CM to be migrated one by one.

  4) Switch from the name 'GCMP' to 'CM' since the Coherence Manager is
     what this code is actually dealing with.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6360/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 786a51ddbb78..be56cd8d213b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -103,6 +103,8 @@ obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_mipsxx.o
 
 obj-$(CONFIG_JUMP_LABEL)	+= jump_label.o
 
+obj-$(CONFIG_MIPS_CM)		+= mips-cm.o
+
 #
 # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
 # safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches