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| author | Maciej W. Rozycki <macro@mips.com> | 2018-05-16 17:39:58 +0200 |
|---|---|---|
| committer | James Hogan <jhogan@kernel.org> | 2018-05-24 15:03:14 +0200 |
| commit | c7e814628df65f424fe197dde73bfc67e4a244d7 (patch) | |
| tree | 50b12208b6edd6f5953348eee071493e7cfe5e30 /arch/mips/kernel/ptrace32.c | |
| parent | MIPS: prctl: Disallow FRE without FR with PR_SET_FP_MODE requests (diff) | |
| download | linux-c7e814628df65f424fe197dde73bfc67e4a244d7.tar.xz linux-c7e814628df65f424fe197dde73bfc67e4a244d7.zip | |
MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs
Use 64-bit accesses for 64-bit floating-point general registers with
PTRACE_PEEKUSR, removing the truncation of their upper halves in the
FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context
access"), which inadvertently switched them to using 32-bit accesses.
The PTRACE_POKEUSR side is fine as it's never been broken and continues
using 64-bit accesses.
Fixes: bbd426f542cb ("MIPS: Simplify FP context access")
Signed-off-by: Maciej W. Rozycki <macro@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/19334/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch/mips/kernel/ptrace32.c')
| -rw-r--r-- | arch/mips/kernel/ptrace32.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index 656a137c1fe2..f30c381d3e1c 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -109,7 +109,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, addr & 1); break; } - tmp = get_fpr32(&fregs[addr - FPR_BASE], 0); + tmp = get_fpr64(&fregs[addr - FPR_BASE], 0); break; case PC: tmp = regs->cp0_epc; |