Merge tag 'for-linus' of https://github.com/openrisc/linux

Pull OpenRISC updates from Stafford Horne:

 - A few sparse warning fixups and other cleanups I noticed when working
   on a recent TLB bug found on a new OpenRISC core bring up.

 - A few fixup's from me and Jason A Donenfeld to help shutdown OpenRISC
   platforms when running CI tests

* tag 'for-linus' of https://github.com/openrisc/linux:
  openrisc: Allow power off handler overriding
  openrisc: Remove unused IMMU tlb workardound
  openrisc/fault: Fix symbol scope warnings
  openrisc/delay: Add include to fix symbol not declared warning
  openrisc/time: Fix symbol scope warnings
  openrisc/traps: Declare unhandled_exception for asmlinkage
  openrisc/traps: Remove die_if_kernel function
  openrisc/traps: Declare file scope symbols as static
  openrisc: Update litex defconfig to support glibc userland
  openrisc: Pretty print show_registers memory dumps
  openrisc: Add syscall details to emergency syscall debugging
  openrisc: Add support for liteuart emergency printing
  openrisc: Cleanup emergency print handling
  openrisc: Add gcc machine instruction flag configuration
  openrisc: define nop command for simulator reboot
  openrisc: remove bogus nops and shutdowns
  openrisc: fix typos in comments

1 files changed, 53 insertions, 0 deletions

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 99f0e4a4cbbd..e814df4c483c 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -113,6 +113,59 @@ config OPENRISC_HAVE_INST_DIV
 	default y
 	help
 	  Select this if your implementation has a hardware divide instruction
+
+config OPENRISC_HAVE_INST_CMOV
+	bool "Have instruction l.cmov for conditional move"
+	default n
+	help
+	  This config enables gcc to generate l.cmov instructions when compiling
+	  the kernel which in general will improve performance and reduce the
+	  binary size.
+
+	  Select this if your implementation has support for the Class II
+	  l.cmov conistional move instruction.
+
+	  Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_ROR
+	bool "Have instruction l.ror for rotate right"
+	default n
+	help
+	  This config enables gcc to generate l.ror instructions when compiling
+	  the kernel which in general will improve performance and reduce the
+	  binary size.
+
+	  Select this if your implementation has support for the Class II
+	  l.ror rotate right instruction.
+
+	  Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_RORI
+	bool "Have instruction l.rori for rotate right with immediate"
+	default n
+	help
+	  This config enables gcc to generate l.rori instructions when compiling
+	  the kernel which in general will improve performance and reduce the
+	  binary size.
+
+	  Select this if your implementation has support for the Class II
+	  l.rori rotate right with immediate instruction.
+
+	  Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_SEXT
+	bool "Have instructions l.ext* for sign extension"
+	default n
+	help
+	  This config enables gcc to generate l.ext* instructions when compiling
+	  the kernel which in general will improve performance and reduce the
+	  binary size.
+
+	  Select this if your implementation has support for the Class II
+	  l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
+
+	  Say N if you are unsure.
+
 endmenu
 
 config NR_CPUS