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| author | Huacai Chen <chenhc@lemote.com> | 2020-05-23 09:56:38 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-06-04 19:51:33 +0200 |
| commit | 7f2a83f1c2a941ebfee53f504ed5fdbc61cfb333 (patch) | |
| tree | d9b831da059d45b689210a8f845a539b9f9c917e /arch/openrisc | |
| parent | KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support (diff) | |
| download | linux-7f2a83f1c2a941ebfee53f504ed5fdbc61cfb333.tar.xz linux-7f2a83f1c2a941ebfee53f504ed5fdbc61cfb333.zip | |
KVM: MIPS: Add CPUCFG emulation for Loongson-3
Loongson-3 overrides lwc2 instructions to implement CPUCFG and CSR
read/write functions. These instructions all cause guest exit so CSR
doesn't benifit KVM guest (and there are always legacy methods to
provide the same functions as CSR). So, we only emulate CPUCFG and let
it return a reduced feature list (which means the virtual CPU doesn't
have any other advanced features, including CSR) in KVM.
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <1590220602-3547-12-git-send-email-chenhc@lemote.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/openrisc')
0 files changed, 0 insertions, 0 deletions