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authorAlexey Kardashevskiy <aik@au1.ibm.com>2011-03-02 16:18:48 +0100
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-27 06:18:19 +0200
commitefcac6589a277c10060e4be44b9455cf43838dc1 (patch)
treed2236c1e9385baff297f0652c5a22b74f6acb149 /arch/powerpc/include/asm/ppc-opcode.h
parentpowerpc/book3e: Flush IPROT protected TLB entries leftover by firmware (diff)
downloadlinux-efcac6589a277c10060e4be44b9455cf43838dc1.tar.xz
linux-efcac6589a277c10060e4be44b9455cf43838dc1.zip
powerpc: Per process DSCR + some fixes (try#4)
The DSCR (aka Data Stream Control Register) is supported on some server PowerPC chips and allow some control over the prefetch of data streams. This patch allows the value to be specified per thread by emulating the corresponding mfspr and mtspr instructions. Children of such threads inherit the value. Other threads use a default value that can be specified in sysfs - /sys/devices/system/cpu/dscr_default. If a thread starts with non default value in the sysfs entry, all children threads inherit this non default value even if the sysfs value is changed later. Signed-off-by: Alexey Kardashevskiy <aik@au1.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/ppc-opcode.h')
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 3e25b258568e..e472659d906c 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -41,6 +41,10 @@
#define PPC_INST_RFCI 0x4c000066
#define PPC_INST_RFDI 0x4c00004e
#define PPC_INST_RFMCI 0x4c00004c
+#define PPC_INST_MFSPR_DSCR 0x7c1102a6
+#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
+#define PPC_INST_MTSPR_DSCR 0x7c1103a6
+#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
#define PPC_INST_STRING 0x7c00042a
#define PPC_INST_STRING_MASK 0xfc0007fe