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| author | Nicholas Piggin <npiggin@gmail.com> | 2017-04-07 03:27:44 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-04-13 15:34:32 +0200 |
| commit | 9b7ff0c6586bc0541ebcd1ff6773b11a49f1a058 (patch) | |
| tree | c7b8f96f7e244d47dd6240e0e06d6929a9bc4cbd /arch/powerpc/include/asm/reg.h | |
| parent | powerpc/64s: Add msgp facility unavailable log string (diff) | |
| download | linux-9b7ff0c6586bc0541ebcd1ff6773b11a49f1a058.tar.xz linux-9b7ff0c6586bc0541ebcd1ff6773b11a49f1a058.zip | |
powerpc/64s: Add SCV FSCR bit for ISA v3.0
Add the bit definition and use it in facility_unavailable_exception() so we can
intelligently report the cause if we take a fault for SCV. This doesn't actually
enable SCV.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Drop whitespace changes to the existing entries, flush out change log]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index d0b332b8afad..4b594ed6180a 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -310,6 +310,7 @@ #define SPRN_PMCR 0x374 /* Power Management Control Register */ /* HFSCR and FSCR bit numbers are the same */ +#define FSCR_SCV_LG 12 /* Enable System Call Vectored */ #define FSCR_MSGP_LG 10 /* Enable MSGP */ #define FSCR_TAR_LG 8 /* Enable Target Address Register */ #define FSCR_EBB_LG 7 /* Enable Event Based Branching */ @@ -320,6 +321,7 @@ #define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ #define FSCR_FP_LG 0 /* Enable Floating Point */ #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ +#define FSCR_SCV __MASK(FSCR_SCV_LG) #define FSCR_TAR __MASK(FSCR_TAR_LG) #define FSCR_EBB __MASK(FSCR_EBB_LG) #define FSCR_DSCR __MASK(FSCR_DSCR_LG) |