diff options
| author | Palmer Dabbelt <palmer@sifive.com> | 2017-12-01 22:10:42 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2017-12-01 22:10:42 +0100 |
| commit | f8182f613c9887744eb469b1a3352636481cb395 (patch) | |
| tree | bb7872d1a46c98aa3fe9cd7c27f24bde1a4d1f90 /arch/riscv/include/asm/tlbflush.h | |
| parent | Linux 4.15-rc1 (diff) | |
| parent | RISC-V: remove spin_unlock_wait() (diff) | |
| download | linux-f8182f613c9887744eb469b1a3352636481cb395.tar.xz linux-f8182f613c9887744eb469b1a3352636481cb395.zip | |
RISC-V Atomic Cleanups
This patch set is the result of some feedback that filtered through
after our original patch set was reviewed, some of which was the result
of me missing some email. It contains:
* A new READ_ONCE in arch_spin_is_locked()
* __test_and_op_bit_ord() is now actually ordered
* Improvements to various comments
* Removal of some dead code
Diffstat (limited to 'arch/riscv/include/asm/tlbflush.h')
| -rw-r--r-- | arch/riscv/include/asm/tlbflush.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 5ee4ae370b5e..c79fab3d377d 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -17,7 +17,10 @@ #ifdef CONFIG_MMU -/* Flush entire local TLB */ +/* + * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction + * cache as well, so a 'fence.i' is not necessary. + */ static inline void local_flush_tlb_all(void) { __asm__ __volatile__ ("sfence.vma" : : : "memory"); |