diff options
| author | Palmer Dabbelt <palmer@sifive.com> | 2018-08-03 21:27:19 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-08-20 19:55:24 +0200 |
| commit | e45c7aca4914efc8bcdd8fc231efadcdc87ae2e5 (patch) | |
| tree | 85dbb9cb9528ce2f392d44db75b8acde5c43cfd2 /arch/riscv/include/uapi | |
| parent | RISC-V: Define sys_riscv_flush_icache when SMP=n (diff) | |
| download | linux-e45c7aca4914efc8bcdd8fc231efadcdc87ae2e5.tar.xz linux-e45c7aca4914efc8bcdd8fc231efadcdc87ae2e5.zip | |
RISC-V: Don't use a global include guard for uapi/asm/syscalls.h
This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables. With
a global include guard we end up missing __NR_riscv_flush_icache in the
syscall table, which results in icache flushes that escape the vDSO call
to not actually do anything.
The fix is to move to per-#define include guards, which allows the
system call tables to actually be populated. Thanks to Macrus Comstedt
for finding and fixing the bug!
Cc: Marcus Comstedt <marcus@mc.pp.se>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include/uapi')
| -rw-r--r-- | arch/riscv/include/uapi/asm/syscalls.h | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/riscv/include/uapi/asm/syscalls.h b/arch/riscv/include/uapi/asm/syscalls.h index 818655b0d535..206dc4b0f6ea 100644 --- a/arch/riscv/include/uapi/asm/syscalls.h +++ b/arch/riscv/include/uapi/asm/syscalls.h @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017 SiFive + * Copyright (C) 2017-2018 SiFive */ -#ifndef _ASM__UAPI__SYSCALLS_H -#define _ASM__UAPI__SYSCALLS_H +/* + * There is explicitly no include guard here because this file is expected to + * be included multiple times in order to define the syscall macros via + * __SYSCALL. + */ /* * Allows the instruction cache to be flushed from userspace. Despite RISC-V @@ -20,7 +23,7 @@ * caller. We don't currently do anything with the address range, that's just * in there for forwards compatibility. */ +#ifndef __NR_riscv_flush_icache #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) -__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) - #endif +__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) |