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| author | Alexandre Ghiti <alexandre.ghiti@canonical.com> | 2021-12-06 11:46:51 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-01-20 02:54:09 +0100 |
| commit | e8a62cc26ddf53a3c6ba2a8d33036cf7b84f3923 (patch) | |
| tree | 15b9020880a651c756268a4560b8c6c720fc1031 /arch/riscv/mm/context.c | |
| parent | asm-generic: Prepare for riscv use of pud_alloc_one and pud_free (diff) | |
| download | linux-e8a62cc26ddf53a3c6ba2a8d33036cf7b84f3923.tar.xz linux-e8a62cc26ddf53a3c6ba2a8d33036cf7b84f3923.zip | |
riscv: Implement sv48 support
By adding a new 4th level of page table, give the possibility to 64bit
kernel to address 2^48 bytes of virtual address: in practice, that offers
128TB of virtual address space to userspace and allows up to 64TB of
physical memory.
If the underlying hardware does not support sv48, we will automatically
fallback to a standard 3-level page table by folding the new PUD level into
PGDIR level. In order to detect HW capabilities at runtime, we
use SATP feature that ignores writes with an unsupported mode.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/mm/context.c')
| -rw-r--r-- | arch/riscv/mm/context.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index ea54cc0c9106..7acbfbd14557 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -192,7 +192,7 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) switch_mm_fast: csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | ((cntx & asid_mask) << SATP_ASID_SHIFT) | - SATP_MODE); + satp_mode); if (need_flush_tlb) local_flush_tlb_all(); @@ -201,7 +201,7 @@ switch_mm_fast: static void set_mm_noasid(struct mm_struct *mm) { /* Switch the page table and blindly nuke entire local TLB */ - csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | SATP_MODE); + csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | satp_mode); local_flush_tlb_all(); } |