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path: root/arch/riscv/mm/context.c (follow)
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* Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements"Palmer Dabbelt2024-04-301-13/+10
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| * riscv: mm: Preserve global TLB entries when switching contextsSamuel Holland2024-04-291-1/+1
| * riscv: mm: Make asid_bits a local variableSamuel Holland2024-04-291-2/+1
| * riscv: mm: Use a fixed layout for the MM context IDSamuel Holland2024-04-291-4/+2
| * riscv: mm: Introduce cntx2asid/cntx2version helper macrosSamuel Holland2024-04-291-6/+6
* | Merge patch series "riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX ...Palmer Dabbelt2024-04-301-8/+11
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| * riscv: Include riscv_set_icache_flush_ctx prctlCharlie Jenkins2024-04-181-8/+11
* | membarrier: riscv: Add full memory barrier in switch_mm()Andrea Parri2024-02-151-0/+2
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* riscv: mm: use bitmap_zero() APIYe Xingchen2023-08-311-1/+1
* riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong2023-03-211-1/+1
* riscv: asid: Fixup stale TLB entry cause application crashGuo Ren2023-03-101-10/+20
* Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich2023-03-101-10/+0
* riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich2022-12-091-0/+10
* riscv: Implement sv48 supportAlexandre Ghiti2022-01-201-2/+2
* riscv: mm: don't advertise 1 num_asid for 0 asid bitsVineet Gupta2021-10-041-3/+5
* riscv: add ASID-based tlbflushing methodsGuo Ren2021-07-011-1/+1
* riscv: mm: Use better bitmap_zalloc()Kefeng Wang2021-06-091-2/+1
* riscv: Add __init section marker to some functions againJisheng Zhang2021-05-291-1/+1
* riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred()Jisheng Zhang2021-05-261-3/+4
* RISC-V: Implement ASID allocatorAnup Patel2021-02-191-4/+261
* riscv: add nommu supportChristoph Hellwig2019-11-181-0/+2
* riscv: add missing header file includesPaul Walmsley2019-10-281-0/+1
* riscv: Using CSR numbers to access CSRsBin Meng2019-08-301-6/+1
* riscv: move switch_mm to its own fileGary Guo2019-05-171-0/+69
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