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authorSreedhara DS <sreedhara.ds@intel.com>2010-07-26 11:03:10 +0200
committerMatthew Garrett <mjg@redhat.com>2010-08-03 15:50:30 +0200
commit804f8681a99da2aa49bd7f0dab3750848d1ab1bc (patch)
tree76bfafe233b4fd93682bbd0a467cce9afc2c7e8f /arch/x86/include/asm/intel_scu_ipc.h
parentintel_scu_ipc: Support Medfield processors (diff)
downloadlinux-804f8681a99da2aa49bd7f0dab3750848d1ab1bc.tar.xz
linux-804f8681a99da2aa49bd7f0dab3750848d1ab1bc.zip
Remove indirect read write api support.
The firmware of production devices does not support this interface so this is dead code. Signed-off-by: Sreedhara DS <sreedhara.ds@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Matthew Garrett <mjg@redhat.com>
Diffstat (limited to 'arch/x86/include/asm/intel_scu_ipc.h')
-rw-r--r--arch/x86/include/asm/intel_scu_ipc.h14
1 files changed, 0 insertions, 14 deletions
diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h
index 03200452069b..29f66793cc55 100644
--- a/arch/x86/include/asm/intel_scu_ipc.h
+++ b/arch/x86/include/asm/intel_scu_ipc.h
@@ -34,20 +34,6 @@ int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);
/* Update single register based on the mask */
int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);
-/*
- * Indirect register read
- * Can be used when SCCB(System Controller Configuration Block) register
- * HRIM(Honor Restricted IPC Messages) is set (bit 23)
- */
-int intel_scu_ipc_register_read(u32 addr, u32 *data);
-
-/*
- * Indirect register write
- * Can be used when SCCB(System Controller Configuration Block) register
- * HRIM(Honor Restricted IPC Messages) is set (bit 23)
- */
-int intel_scu_ipc_register_write(u32 addr, u32 data);
-
/* Issue commands to the SCU with or without data */
int intel_scu_ipc_simple_command(int cmd, int sub);
int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,