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| author | Jacob Pan <jacob.jun.pan@linux.intel.com> | 2024-04-23 19:41:08 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-04-30 00:54:42 +0200 |
| commit | 43650dcf6d6322ec2d0938bb51f755810ffa783a (patch) | |
| tree | 2cd02699df1c194b5e3a0749d6a89f3e4d7d2a87 /arch/x86/kernel/cpu/common.c | |
| parent | x86/irq: Reserve a per CPU IDT vector for posted MSIs (diff) | |
| download | linux-43650dcf6d6322ec2d0938bb51f755810ffa783a.tar.xz linux-43650dcf6d6322ec2d0938bb51f755810ffa783a.zip | |
x86/irq: Set up per host CPU posted interrupt descriptors
To support posted MSIs, create a posted interrupt descriptor (PID) for each
host CPU. Later on, when setting up interrupt affinity, the IOMMU's
interrupt remapping table entry (IRTE) will point to the physical address
of the matching CPU's PID.
Each PID is initialized with the owner CPU's physical APICID as the
destination.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240423174114.526704-7-jacob.jun.pan@linux.intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/common.c')
| -rw-r--r-- | arch/x86/kernel/cpu/common.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 605c26c009c8..25ef145586c6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -68,6 +68,7 @@ #include <asm/traps.h> #include <asm/sev.h> #include <asm/tdx.h> +#include <asm/posted_intr.h> #include "cpu.h" @@ -2227,6 +2228,8 @@ void cpu_init(void) barrier(); x2apic_setup(); + + intel_posted_msi_init(); } mmgrab(&init_mm); |