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| author | Peter Zijlstra <peterz@infradead.org> | 2023-08-07 14:38:07 +0200 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2023-08-09 21:51:06 +0200 |
| commit | 882cdb06b668488a42ef717a260c05ba7dc43a49 (patch) | |
| tree | 4d727488dd22489c176cac9a20b7032002f40d56 /arch/x86/kernel/cpu/intel_epb.c | |
| parent | perf: Remove unused extern declaration arch_perf_get_page_size() (diff) | |
| download | linux-882cdb06b668488a42ef717a260c05ba7dc43a49.tar.xz linux-882cdb06b668488a42ef717a260c05ba7dc43a49.zip | |
x86/cpu: Fix Gracemont uarch
Alderlake N is an E-core only product using Gracemont
micro-architecture. It fits the pre-existing naming scheme perfectly
fine, adhere to it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20230807150405.686834933@infradead.org
Diffstat (limited to 'arch/x86/kernel/cpu/intel_epb.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel_epb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c index 3b8476158236..e4c3ba91321c 100644 --- a/arch/x86/kernel/cpu/intel_epb.c +++ b/arch/x86/kernel/cpu/intel_epb.c @@ -206,7 +206,7 @@ static int intel_epb_offline(unsigned int cpu) static const struct x86_cpu_id intel_epb_normal[] = { X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, ENERGY_PERF_BIAS_NORMAL_POWERSAVE), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, ENERGY_PERF_BIAS_NORMAL_POWERSAVE), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, ENERGY_PERF_BIAS_NORMAL_POWERSAVE), |