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| author | Yann Gautier <yann.gautier@st.com> | 2019-11-06 11:09:36 +0100 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@st.com> | 2019-12-09 09:19:15 +0100 |
| commit | 64e11cb783d120d0a76cf89dbe4471ba98db0d8a (patch) | |
| tree | 2f208c3aff30d195c782a289e420674e713c662e /arch | |
| parent | ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157 (diff) | |
| download | linux-64e11cb783d120d0a76cf89dbe4471ba98db0d8a.tar.xz linux-64e11cb783d120d0a76cf89dbe4471ba98db0d8a.zip | |
ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC
The STM32MP157 SoC series includes 3 instances of the SDMMC peripheral.
The sdmmc2 and sdmmc3 nodes are added in STM32MP157 SoC DT file.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/stm32mp157c.dtsi | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 901db8a4abf4..d3a9791a0fda 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -1060,6 +1060,21 @@ }; }; + sdmmc3: sdmmc@48004000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48004000 0x400>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC3_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + usbotg_hs: usb-otg@49000000 { compatible = "snps,dwc2"; reg = <0x49000000 0x10000>; @@ -1348,13 +1363,29 @@ arm,primecell-periphid = <0x10153180>; reg = <0x58005000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + status = "disabled"; + }; + + sdmmc2: sdmmc@58007000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x58007000 0x1000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; }; crc1: crc@58009000 { |