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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2019-11-19 18:53:18 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2019-12-11 10:19:10 +0100 |
| commit | 88432f5f8469ba67a2e20aeda04bd64cb88f9c6c (patch) | |
| tree | a03db8ee1d2ed1b4e61aa597c635b6504262a500 /arch | |
| parent | dt-bindings: pwm: allwinner: Add H6 PWM description (diff) | |
| download | linux-88432f5f8469ba67a2e20aeda04bd64cb88f9c6c.tar.xz linux-88432f5f8469ba67a2e20aeda04bd64cb88f9c6c.zip | |
arm64: dts: allwinner: h6: Add PWM node
Allwinner H6 PWM is similar to that in A20 except that it has additional
bus clock and reset line.
Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 24ffe2dcbddb..83f98bd75ee6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -255,6 +255,16 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; |