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authorGeert Uytterhoeven <geert+renesas@glider.be>2024-05-29 14:07:42 +0200
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2024-06-10 13:01:31 +0200
commit8ede71e1202011d8bfceeab4737e6d52d88688ab (patch)
tree2a5363c5df1604fe0a983014247375d91df56dbf /arch
parentARM: 9400/1: Remove unused struct 'mod_unwind_map' (diff)
downloadlinux-8ede71e1202011d8bfceeab4737e6d52d88688ab.tar.xz
linux-8ede71e1202011d8bfceeab4737e6d52d88688ab.zip
ARM: 9402/1: Kconfig: Spelling s/Cortex A-/Cortex-A/
Fix a misspelling of "Cortex-A9", to make it easier to find which errata are applicable to Cortex-A9 CPU cores. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ee5115252aac..9e0749b22446 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -735,7 +735,7 @@ config ARM_ERRATA_764319
bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
depends on CPU_V7
help
- This option enables the workaround for the 764319 Cortex A-9 erratum.
+ This option enables the workaround for the 764319 Cortex-A9 erratum.
CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
unexpected Undefined Instruction exception when the DBGSWENABLE
external pin is set to 0, even when the CP14 accesses are performed