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| author | Florian Fainelli <f.fainelli@gmail.com> | 2020-08-19 20:26:44 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-21 09:28:43 +0200 |
| commit | dbfc95f98f0158958d1f1e6bf06d74be38dbd821 (patch) | |
| tree | 41121a4e3c5770976ac2dfcc4f882ae54f144ff5 /arch | |
| parent | MIPS: Loongson64: Do not override watch and ejtag feature (diff) | |
| download | linux-dbfc95f98f0158958d1f1e6bf06d74be38dbd821.tar.xz linux-dbfc95f98f0158958d1f1e6bf06d74be38dbd821.zip | |
MIPS: mm: BMIPS5000 has inclusive physical caches
When the BMIPS generic cpu-feature-overrides.h file was introduced,
cpu_has_inclusive_caches/MIPS_CPU_INCLUSIVE_CACHES was not set for
BMIPS5000 CPUs. Correct this when we have initialized the MIPS secondary
cache successfully.
Fixes: f337967d6d87 ("MIPS: BMIPS: Add cpu-feature-overrides.h")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index fc5a6d25f74f..0ef717093262 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1712,7 +1712,11 @@ static void setup_scache(void) printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + + if (current_cpu_type() == CPU_BMIPS5000) + c->options |= MIPS_CPU_INCLUSIVE_CACHES; } + #else if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); |