diff options
| author | Luca Weiss <luca.weiss@fairphone.com> | 2021-12-13 09:26:11 +0100 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2021-12-13 23:56:10 +0100 |
| commit | f56498fc6a9364a35dd74af791bd1251467e9cc1 (patch) | |
| tree | 1cc34dedc588ae8fd764d6b5d77b58da33063c88 /arch | |
| parent | arm64: dts: qcom: Add device tree for Samsung J5 2015 (samsung-j5) (diff) | |
| download | linux-f56498fc6a9364a35dd74af791bd1251467e9cc1.tar.xz linux-f56498fc6a9364a35dd74af791bd1251467e9cc1.zip | |
arm64: dts: qcom: sm6350: Fix validation errors
Sort clocks and interrupts as specified in the docs and remove the stray
property #power-domain-cells from aoss_qmp to solve dtbs_check
validation errors.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211213082614.22651-11-luca.weiss@fairphone.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6350.dtsi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index cd55797facf6..14e1071bcca4 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -531,10 +531,10 @@ ranges; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&xo_board>, <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&xo_board>; - clock-names = "aux", "ref", "com_aux", "cfg_ahb"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; @@ -592,11 +592,12 @@ "sleep"; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -656,7 +657,6 @@ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; - #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { |