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| author | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 2017-04-14 17:04:32 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-07-03 01:47:39 +0200 |
| commit | 9a181e1093af59f53eaa33bcd2281a0a2158a7be (patch) | |
| tree | 653ebdd04850ca28ba74a4026cf650db155be693 /block/partitions | |
| parent | arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq() (diff) | |
| download | linux-9a181e1093af59f53eaa33bcd2281a0a2158a7be.tar.xz linux-9a181e1093af59f53eaa33bcd2281a0a2158a7be.zip | |
PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts
- Add spinlock for protecting legacy mask register
- Few wifi end points which only support legacy interrupts, performs
hardware reset functionalities after disabling interrupts by invoking
disable_irq() and then re-enable using enable_irq(), they enable hardware
interrupts first and then virtual IRQ line later.
- The legacy IRQ line goes low only after DEASSERT_INTx is received. As
the legacy IRQ line is high immediately after hardware interrupts are
enabled but virq of EP is still in disabled state and EP handler is never
executed resulting no DEASSERT_INTx. If dummy IRQ chip is used,
interrupts are not masked and system hangs with CPU stall.
- Add IRQ chip functions instead of dummy IRQ chip for legacy interrupts.
- Legacy interrupts are level sensitive, so using handle_level_irq() is
more appropriate as it is masks interrupts until Endpoint handles
interrupts and unmasks interrupts after Endpoint handler is executed.
- Legacy interrupts are level triggered, virtual IRQ line of EndPoint shows
as edge in /proc/interrupts.
- Set IRQ flags of virtual IRQ line of EP to level triggered at the time of
mapping.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'block/partitions')
0 files changed, 0 insertions, 0 deletions