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author | Stephen Boyd <sboyd@kernel.org> | 2019-03-08 19:27:52 +0100 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2019-03-08 19:27:52 +0100 |
commit | 461ea6ab2c49177bcc7b5a8aa54d614099668815 (patch) | |
tree | b4adb29883a575a138ab6e8f069462764e9a9ac5 /drivers/clk/clk-qoriq.c | |
parent | Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and 'c... (diff) | |
parent | clk: qcom: clk-rpmh: Add IPA clock support (diff) | |
parent | clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk (diff) | |
parent | dt-bindings: clock: remove unused definition for stm32mp1 (diff) | |
parent | clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock (diff) | |
parent | clk: actions: Add clock driver for S500 SoC (diff) | |
download | linux-461ea6ab2c49177bcc7b5a8aa54d614099668815.tar.xz linux-461ea6ab2c49177bcc7b5a8aa54d614099668815.zip |
Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', 'clk-qcom-qcs404' and 'clk-actions-s500' into clk-next
- IPA clk support on Qualcomm RPMh clk controllers
- Support sleeping gpios in clk-gpio type
- Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
- Actions Semi S500 SoC clk support
* clk-qcom-rpmh:
clk: qcom: clk-rpmh: Add IPA clock support
* clk-gpio-sleep:
clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk
* clk-stm32mp1:
dt-bindings: clock: remove unused definition for stm32mp1
clk: stm32mp1: fix bit width of hse_rtc divider
clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
clk: stm32mp1: fix HSI divider flag
clk: stm32mp1: fix mcu divider table
clk: stm32mp1: set ck_csi as critical clock
clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
clk: stm32mp1: parent clocks update
* clk-qcom-qcs404:
clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs
clk: qcom: remove empty lines in clk-rcg.h
* clk-actions-s500:
clk: actions: Add clock driver for S500 SoC
dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU
clk: actions: Add configurable PLL delay