diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 15:58:43 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:04:03 +0100 |
| commit | d610b54f77002bbddca54c10d9488c2faa7ff102 (patch) | |
| tree | a991e55607dc05c8f35690122bb66dad30ae55ec /drivers/clk/meson/gxbb.h | |
| parent | clk: meson: migrate plls clocks to clk_regmap (diff) | |
| download | linux-d610b54f77002bbddca54c10d9488c2faa7ff102.tar.xz linux-d610b54f77002bbddca54c10d9488c2faa7ff102.zip | |
clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.
This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb.h')
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 42573b28a137..a8e7b8884e95 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -195,8 +195,11 @@ #define CLKID_VAPB_0_DIV 134 #define CLKID_VAPB_1_DIV 137 #define CLKID_HDMI_PLL_PRE_MULT 141 +#define CLKID_MPLL0_DIV 142 +#define CLKID_MPLL1_DIV 143 +#define CLKID_MPLL2_DIV 144 -#define NR_CLKS 142 +#define NR_CLKS 145 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/gxbb-clkc.h> |