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| author | Stephen Boyd <sboyd@kernel.org> | 2024-01-09 20:52:35 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-01-09 20:52:35 +0100 |
| commit | 8066514dc53dd649be6b24a7a92c3602d42357d7 (patch) | |
| tree | 067515a7ecff3e06a8e170a95e780faebdc36414 /drivers/clk/qcom/apss-ipq-pll.c | |
| parent | Merge branches 'clk-renesas', 'clk-rockchip', 'clk-allwinner' and 'clk-cleanu... (diff) | |
| parent | clk: versaclock3: Drop ret variable (diff) | |
| parent | clk: si5351: allow PLLs to be adjusted without reset (diff) | |
| parent | Merge tag 'samsung-clk-6.8' of https://git.kernel.org/pub/scm/linux/kernel/gi... (diff) | |
| parent | clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx (diff) | |
| parent | dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC (diff) | |
| download | linux-8066514dc53dd649be6b24a7a92c3602d42357d7.tar.xz linux-8066514dc53dd649be6b24a7a92c3602d42357d7.zip | |
Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and 'clk-sophgo' into clk-next
- Add glitch free PLL setting support to si5351 clk driver
* clk-versa:
clk: versaclock3: Drop ret variable
clk: versaclock3: Add missing space between ')' and '{'
clk: versaclock3: Use u8 return type for get_parent() callback
clk: versaclock3: Avoid unnecessary padding
clk: versaclock3: Update vc3_get_div() to avoid divide by zero
* clk-silabs:
clk: si5351: allow PLLs to be adjusted without reset
dt-bindings: clock: si5351: add PLL reset mode property
dt-bindings: clock: si5351: convert to yaml
* clk-samsung:
clk: samsung: Improve kernel-doc comments
clk: samsung: Fix kernel-doc comments
* clk-starfive:
clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
clk: starfive: Add flags argument to JH71X0__MUX macro
* clk-sophgo:
dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC