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authorKoji Matsuoka <koji.matsuoka.xm@renesas.com>2017-04-19 19:46:26 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-05-15 09:46:31 +0200
commit12390605ac55e686af93140553d3c74c56ac4dc3 (patch)
tree338781c700c7a95b8b77b58fcf035f559f4aca56 /drivers/clk/renesas/r8a7796-cpg-mssr.c
parentclk: renesas: r8a7795: Add HS-USB ch3 clock (diff)
downloadlinux-12390605ac55e686af93140553d3c74c56ac4dc3.tar.xz
linux-12390605ac55e686af93140553d3c74c56ac4dc3.zip
clk: renesas: r8a7796: Add HDMI clock
This patch adds HDMI-IF0 clock for R8A7796 SoC. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7796-cpg-mssr.c')
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 9d114b31b073..1d8c5c2b6174 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -106,6 +106,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+ DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -170,6 +171,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
+ DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),