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authorMaxime Ripard <maxime@cerno.tech>2021-05-11 13:35:52 +0200
committerMaxime Ripard <maxime@cerno.tech>2021-05-11 13:35:52 +0200
commitc55b44c9386f3ee1b08752638559f19deaf6040d (patch)
treec843a21f45180387fcd9eb2625cc9d1f166a3156 /drivers/clk/renesas/r8a779a0-cpg-mssr.c
parentMAINTAINERS: Update my e-mail (diff)
parentLinux 5.13-rc1 (diff)
downloadlinux-c55b44c9386f3ee1b08752638559f19deaf6040d.tar.xz
linux-c55b44c9386f3ee1b08752638559f19deaf6040d.zip
Merge drm/drm-fixes into drm-misc-fixes
Start this new release drm-misc-fixes branch Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/clk/renesas/r8a779a0-cpg-mssr.c')
-rw-r--r--drivers/clk/renesas/r8a779a0-cpg-mssr.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index f23fe9d5e5e1..867c565cb58f 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -144,6 +144,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
@@ -192,6 +193,11 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2),
DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2),
+ DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK),
+ DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4),
+ DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4),
+ DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4),
+ DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4),
DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1),
DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1),
DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
@@ -227,10 +233,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1),
DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1),
DEF_MOD("rwdt", 907, R8A779A0_CLK_R),
+ DEF_MOD("cmt0", 910, R8A779A0_CLK_R),
+ DEF_MOD("cmt1", 911, R8A779A0_CLK_R),
+ DEF_MOD("cmt2", 912, R8A779A0_CLK_R),
+ DEF_MOD("cmt3", 913, R8A779A0_CLK_R),
DEF_MOD("pfc0", 915, R8A779A0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
+ DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK),
DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),