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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-05-10 13:06:53 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-06 11:13:30 +0200 |
| commit | b6ee0bbf388ab38384f92339aa9a1df15e716cfe (patch) | |
| tree | 080358cffa365d3cf0f196efcb412145c46f6465 /drivers/clk/renesas/r9a09g011-cpg.c | |
| parent | clk: renesas: r9a07g044: Add GPT clock and reset entry (diff) | |
| download | linux-b6ee0bbf388ab38384f92339aa9a1df15e716cfe.tar.xz linux-b6ee0bbf388ab38384f92339aa9a1df15e716cfe.zip | |
clk: renesas: r9a07g044: Add POEG clock and reset entries
Add POEG clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220510110653.7326-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r9a09g011-cpg.c')
0 files changed, 0 insertions, 0 deletions