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path: root/drivers/clk/renesas/r9a09g011-cpg.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: r9a09g011: Add CSI related clocksFabrizio Castro2023-07-101-0/+15
* clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy2022-12-271-0/+20
* clk: renesas: r9a09g011: Add USB clock and reset entriesBiju Das2022-12-271-0/+21
* clk: renesas: r9a09g011: Add TIM clock and reset entriesBiju Das2022-12-271-0/+22
* clk: renesas: r9a09g011: Add PWM clock and reset entriesBiju Das2022-12-261-0/+10
* clk: renesas: r9a09g011: Add IIC clock and reset entriesPhil Edworthy2022-08-291-0/+4
* clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy2022-06-061-0/+3
* clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy2022-06-061-0/+2
* clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy2022-05-061-5/+9
* clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy2022-05-061-0/+168