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authorBiju Das <biju.das.jz@bp.renesas.com>2022-04-12 18:13:12 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-04-13 12:29:08 +0200
commitc8b088224c25ef4f5270f9de6a3516181b63f38c (patch)
tree96b70a069c80c912b7d1db56bd3e199c06f015dd /drivers/clk/renesas/rzg2l-cpg.c
parentMerge tag 'renesas-r9a07g043-dt-binding-defs-tag' into renesas-clk-for-v5.19 (diff)
downloadlinux-c8b088224c25ef4f5270f9de6a3516181b63f38c.tar.xz
linux-c8b088224c25ef4f5270f9de6a3516181b63f38c.zip
clk: renesas: Add support for RZ/G2UL SoC
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are not present on RZ/G2UL. This patch adds minimal clock and reset entries required to boot the system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.c')
-rw-r--r--drivers/clk/renesas/rzg2l-cpg.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index f626d2704477..1ce35f65682b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -945,6 +945,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
}
static const struct of_device_id rzg2l_cpg_match[] = {
+#ifdef CONFIG_CLK_R9A07G043
+ {
+ .compatible = "renesas,r9a07g043-cpg",
+ .data = &r9a07g043_cpg_info,
+ },
+#endif
#ifdef CONFIG_CLK_R9A07G044
{
.compatible = "renesas,r9a07g044-cpg",