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authorXing Zheng <zhengxing@rock-chips.com>2015-11-05 08:33:58 +0100
committerHeiko Stuebner <heiko@sntech.de>2015-11-23 21:59:19 +0100
commit5190c08b29899131a183ea5802b9397918cca1ae (patch)
tree3a052d259e110217fd4ef284395cfd28e68eb46e /drivers/clk/rockchip/clk.h
parentclk: rockchip: add new pll-type for rk3036 and similar socs (diff)
downloadlinux-5190c08b29899131a183ea5802b9397918cca1ae.tar.xz
linux-5190c08b29899131a183ea5802b9397918cca1ae.zip
clk: rockchip: add clock controller for rk3036
Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
-rw-r--r--drivers/clk/rockchip/clk.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 61e7b2d995f1..8d8f942ae7fc 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -33,7 +33,7 @@ struct clk;
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
-/* register positions shared by RK2928, RK3066 and RK3188 */
+/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
@@ -43,6 +43,13 @@ struct clk;
#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
#define RK2928_MISC_CON 0x134
+#define RK3036_SDMMC_CON0 0x144
+#define RK3036_SDMMC_CON1 0x148
+#define RK3036_SDIO_CON0 0x14c
+#define RK3036_SDIO_CON1 0x150
+#define RK3036_EMMC_CON0 0x154
+#define RK3036_EMMC_CON1 0x158
+
#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3288_MODE_CON 0x50
#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)