| Commit message (Expand) | Author | Age | Files | Lines |
* | clk: rockchip: Optimize PLL table memory usage | Elaine Zhang | 2021-05-11 | 1 | -11/+18 |
* | clk: rockchip: add clock controller for rk3568 | Elaine Zhang | 2021-03-21 | 1 | -1/+29 |
* | clk: rockchip: support more core div setting | Elaine Zhang | 2021-03-21 | 1 | -11/+13 |
* | clk: rockchip: Add clock controller for the rk3308 | Finley Xiao | 2019-09-05 | 1 | -0/+13 |
* | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2019-07-17 | 1 | -0/+4 |
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| * | clk: rockchip: add a type from SGRF-controlled gate clocks | Heiko Stuebner | 2019-06-14 | 1 | -0/+4 |
* | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 2019-05-30 | 1 | -10/+1 |
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* | clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type | Finley Xiao | 2019-04-12 | 1 | -0/+23 |
* | clk: rockchip: add clock controller for px30 | Elaine Zhang | 2018-07-06 | 1 | -1/+40 |
* | clk: rockchip: add support for half divider | Elaine Zhang | 2018-07-06 | 1 | -0/+85 |
* | clk: rockchip: rename RK1108 to RV1108 | Andy Yan | 2017-03-22 | 1 | -14/+14 |
* | clk: rockchip: add clock controller for rk3328 | Elaine Zhang | 2017-01-05 | 1 | -0/+18 |
* | clk: rockchip: add new pll-type for rk3328 | Elaine Zhang | 2017-01-02 | 1 | -0/+1 |
* | clk: rockchip: add a clock-type for muxes based in the grf | Heiko Stuebner | 2017-01-02 | 1 | -0/+21 |
* | clk: rockchip: add clock controller for rk1108 | Shawn Lin | 2016-11-16 | 1 | -0/+15 |
* | clk: rockchip: add new clock-type for the ddrclk | Lin Huang | 2016-09-01 | 1 | -0/+33 |
* | clk: rockchip: use general clock flag when registering pll | Heiko Stübner | 2016-08-08 | 1 | -1/+1 |
* | clk: rockchip: simplify GRF handling in pll clocks | Heiko Stuebner | 2016-05-09 | 1 | -1/+0 |
* | clk: rockchip: fix checkpatch warning in core code | Heiko Stuebner | 2016-04-20 | 1 | -1/+1 |
* | clk: rockchip: drop unnecessary header comment | Heiko Stuebner | 2016-04-19 | 1 | -1/+0 |
* | clk: rockchip: add clock controller for the RK3399 | Xing Zheng | 2016-03-28 | 1 | -1/+21 |
* | clk: rockchip: fix warning reported by kernel-doc | Shawn Lin | 2016-03-27 | 1 | -4/+5 |
* | clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data | Shawn Lin | 2016-03-27 | 1 | -1/+0 |
* | clk: rockchip: add new pll-type for rk3399 and similar socs | Xing Zheng | 2016-03-27 | 1 | -1/+2 |
* | clk: rockchip: Add support for multiple clock providers | Xing Zheng | 2016-03-27 | 1 | -13/+38 |
* | clk: rockchip: allow varying mux parameters for cpuclk pll-sources | Xing Zheng | 2016-03-27 | 1 | -0/+6 |
* | clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type | Xing Zheng | 2016-03-27 | 1 | -0/+16 |
* | clk: rockchip: add a factor clock type | Heiko Stuebner | 2016-02-04 | 1 | -0/+28 |
* | Merge branch 'clk-rockchip' into clk-next | Michael Turquette | 2016-01-02 | 1 | -1/+1 |
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| * | clk: rockchip: fix section mismatches with new child-clocks | Heiko Stübner | 2016-01-02 | 1 | -1/+1 |
* | | Merge branch 'clk-rockchip' into clk-next | Michael Turquette | 2015-12-23 | 1 | -0/+19 |
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| * | clk: rockchip: handle mux dependency of fractional dividers | Heiko Stuebner | 2015-12-23 | 1 | -0/+19 |
* | | clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 | Heiko Stuebner | 2015-12-21 | 1 | -1/+1 |
* | | clk: rockchip: add clock controller for rk3228 | Jeffy Chen | 2015-12-12 | 1 | -1/+10 |
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* | clk: rockchip: add clock controller for rk3036 | Xing Zheng | 2015-11-23 | 1 | -1/+8 |
* | clk: rockchip: add new pll-type for rk3036 and similar socs | Xing Zheng | 2015-11-23 | 1 | -0/+23 |
* | clk: rockchip: Fix PLL bandwidth | Douglas Anderson | 2015-07-28 | 1 | -4/+4 |
* | Merge branch 'cleanup-clk-h-includes' into clk-next | Stephen Boyd | 2015-07-28 | 1 | -2/+2 |
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| * | clk: rockchip: Properly include clk.h | Stephen Boyd | 2015-07-20 | 1 | -2/+2 |
* | | clk: rockchip: add rk3368 clock controller | Heiko Stuebner | 2015-07-07 | 1 | -0/+16 |
* | | clk: rockchip: add support for phase inverters | Heiko Stuebner | 2015-07-07 | 1 | -0/+20 |
* | | clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant | Heiko Stuebner | 2015-07-07 | 1 | -0/+20 |
* | | clk: rockchip: protect register macros against multipart values | Heiko Stuebner | 2015-07-07 | 1 | -8/+8 |
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* | clk: make several parent names const | Uwe Kleine-König | 2015-06-04 | 1 | -10/+10 |
* | clk: don't use __initconst for non-const arrays | Uwe Kleine-König | 2015-04-13 | 1 | -2/+2 |
* | clk: rockchip: Add support for the mmc clock phases using the framework | Alexandru M Stan | 2014-11-28 | 1 | -0/+23 |
* | clk: rockchip: add optional sync to pll rate parameters | Heiko Stuebner | 2014-11-25 | 1 | -0/+6 |
* | clk: rockchip: add ability to specify pll-specific flags | Heiko Stuebner | 2014-11-25 | 1 | -2/+5 |
* | clk: rockchip: change PLL setting for better clock jitter | Kever Yang | 2014-10-29 | 1 | -0/+9 |
* | clk: rockchip: add restart handler | Heiko Stübner | 2014-10-01 | 1 | -0/+1 |