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authorHeiko Stuebner <heiko@sntech.de>2019-06-14 10:59:48 +0200
committerHeiko Stuebner <heiko@sntech.de>2019-06-27 11:02:28 +0200
commit794e94ca83450c436313df18291e139cf5f9121f (patch)
tree74c172fedb11e81f899b4729ef36f0145b161bf8 /drivers/clk/rockchip
parentclk: rockchip: add watchdog pclk on rk3328 (diff)
downloadlinux-794e94ca83450c436313df18291e139cf5f9121f.tar.xz
linux-794e94ca83450c436313df18291e139cf5f9121f.zip
clk: rockchip: export HDMIPHY clock on rk3228
Export the hdmiphy clock mux via the newly added clock-id. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Justin Swartz <justin.swartz@risingedge.co.za>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 0801da8b1ed6..68bf4f8fd64c 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -256,7 +256,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(4), 0, GFLAGS),
/* PD_MISC */
- MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
+ MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 13, 1, MFLAGS),
MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 14, 1, MFLAGS),