diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2020-03-03 20:29:56 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-03-06 21:06:01 +0100 |
| commit | d894992502474a6e84644012deb14a0280acbf96 (patch) | |
| tree | 84fa396ebf33c06c1117ca1b37f540935e8b03d1 /drivers/clk/rockchip | |
| parent | clk: Fix phase init check (diff) | |
| download | linux-d894992502474a6e84644012deb14a0280acbf96.tar.xz linux-d894992502474a6e84644012deb14a0280acbf96.zip | |
clk: rockchip: fix mmc get phase
If the mmc clock has no rate, it can be assumed to be constant.
In such case, there is no measurable phase shift. Just return 0
in this case instead of returning an error.
Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration")
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-mmc-phase.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c index 4abe7ff31f53..975454a3dd72 100644 --- a/drivers/clk/rockchip/clk-mmc-phase.c +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -51,9 +51,9 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) u16 degrees; u32 delay_num = 0; - /* See the comment for rockchip_mmc_set_phase below */ + /* Constant signal, no measurable phase shift */ if (!rate) - return -EINVAL; + return 0; raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); |